a³ release 10.04

New target

Qualification Support Kits (QSKs)

  • Original measurements contained in QSKs.
  • New QSK available for the aiT module of a³ for PPC750.

a³ launcher

  • Improved XTC 2.0 support.
  • Extended XTC 1.0 support.
  • Improved batch mode.
  • New command line option -B for interactive batch mode.
  • New command line option -i to start specific analyses in batch mode.
  • Improved handling of XTC requests. Global settings are propagated to following analyses, to avoid the need of reconfiguring the target for each analysis.

a³ toolchain

  • XML reports are now generated for each analysis separately (see screenshot). There is no global XML report anymore.
  • XML reports now include notes, infos, warnings and errors (but no progress and debug messages).
  • Text reports are now also available for each analysis separately, in addition to global text reports.
  • a³ works on projects located on network shares accessed via UNC paths.
  • The intermediate files used during the analyses (CRL files, section files, DWARF debug info) are now compressed with zlib.
  • Output correct types for analysis results in XML results file.
  • Mini-dump support for complete tool-chain, if abnormal program terminations occur.
  • Better checking of available main memory for analysis. For example, the user cannot specify more memory to use than the machine has.
  • For convenience reasons, the tool chain no longer floods the user with identical messages, such as write accesses into read-only memory regions. This behavior is configurable in the a³ GUI. See screenshot.
  • Improved detection of multiple disjoint precise memory accesses.

Visualization

  • Improved source code visualisation in graphs.
  • Extended PDF output functionality.

a³ GUI

  • The performance of the a³ GUI has been greatly improved for large project files with multiple analyses.
  • Content of data sections only visible in Sections view, no longer in Disassembly view. This will increase the speed of the disassembly browser and decrease memory usage.
  • New command line option -B for interactive batch mode.
  • New command line option -i to start specific analyses in batch mode.
  • All-new Global Preferences dialog. See screenshot.
  • Debug view:
    • Improved speed and memory consumption of debug view for variables and functions.
    • When searching in the Debug view, the results are now filtered rather than highlighted.
  • Enhanced readability of Disassembly view.
  • On opening examples, a³ now offers the option of copying standard examples to a directory where the user can modify them.
  • Improved speed of debugging reader, avoiding freezes during project load.
  • Changed advanced analysis options:
    • “Maximum Memory Usage” now set in percentages (1–100%, default is 50%) instead of hard memory sizes. This allows better portability of a project from one machine to another. Old settings will be imported, “automatic” will be translated to 100%, otherwise percentage of RAM of machine is calculated and stored.
    • Changed “Widening Threshold” to “Enable Widening For Cache States”, only allowing to activate (default) or deactivate this. For most complex architectures, deactivation will lead to high memory consumption and very long analysis time. Old settings will be imported; if a widening threshold other than 0 was specified, it will be translated to “activated”.
  • Greatly simplified the email-based license request process. See screenshot.
  • Any background activity (e.g., extraction of symbols) is now made visible by means of a small widget. See screenshot.
  • “Collapse all” context menu entry to remove all splitters.
  • Re-enabled import of control files (generated by old aiT GUI) under “Analyses” → “Overview”. See screenshot.
  • The section dialog now shows the address of a byte within the section, when hovering over that byte.
  • Projects can now be exported to a target directory or a ZIP file. This feature comes in handy when exchanging project data.
  • Interactive analysis results can now be converted into AIS annotations that can be used for further analyses.
  • The user can now clone existing analyses on the Analyses Overview page.
  • WCET analysis: in the new section “WCET Contributions”, a table with cumulative WCET contributions for each routine can be viewed. See screenshot.
  • Improved search in the disassembly view.
  • Improved handling of multiple configurations inside one project. See screenshot.
  • Instructions annotated in the AIS file are now highlighted throughout the GUI:
    • in the Graph view on instruction level
    • in the Disassembly view
    • in the Source Files view
    See screenshots. The highlighted instructions are also linked to the corresponding line in the AIS file.
  • a³ now officially supports the XTC exchange format. The user may generate XTC requests and import XTC responses. So far only T1 is supported. T1 can measure unknown loop bounds (and, in the future, targets of unresolved computed calls). See screenshot.
  • If the specified machine settings file does not exist, the manually specified machine settings are now taken without a warning.
  • Fixed possible a³ crash if analysis name is changed.
  • Fixed problem with multiple warnings about not writable project directory.
  • Correctly handle paged addresses in the Sections view.
  • Improved sorting of entries in the Symbol view.
  • Old analysis results are deleted from the Overview page on analysis re-start.
  • Am486, i386:
    • User can now set up TSS address.
    • Improved import of legacy APF project files.

a³ GUI — Graph view

  • It is now possible to quickly jump between functions by using a drop-down menu in the bottom right corner of the window. The function that is currently in focus in the graph window is always automatically pre-selected in the drop-down menu. See screenshot.
  • Show the correct graph when entering the panner mode.
  • Better interaction between Graph view and Source Code view.
  • Neighbors of instruction nodes can now be quickly navigated to via the entry “Goto neighbor” in the context menu. This is especially useful for jumping between the start and end instruction of a large loop that doesn’t completely fit into the graph window.

a³ GUI — text editor

  • Printing functionality has been added to the text editors.
  • Improved AIS syntax highlighting. See screenshot.
  • Improved handling of relative filenames in the AIS editor.
  • The GUI now shows the absolute paths of opened files (e.g., edited AIS files).
  • Improved usability of the AIS file editor.
  • “File modified” warnings caused by multiple AIS file editor instances are now avoided by sharing the AIS editor widgets among the project instance.

AIS

  • Additional start points for the analysis can now be specified, for example to compute WCETs of subroutines: 
    routine "R" is additional start;
    For each start point (main start point plus additional start points), aiT performs a separate cache and pipeline analysis, followed by path analysis and visualization of results. Each of the separate analyses uses the common value analysis information computed from the main start point. For further information, refer to the user manual, section “Additional Start Points for Timing Analysis”.
  • Stack analysis: descriptions of calls or branches via arrays/tables may now involve indirections. Arrays may be null-terminated, and the access may be restricted to special indices. For further information, refer to the user manual, section “Indirect Calls or Branches via Arrays of Function Pointers or Switch Tables”.
  • There is an incompatible syntax change regarding the request of “WCET contribution of code snippets”. For instance, 
    SNIPPET P1 .. P2 IS EVALUATED AS "Name";
    should be replaced by 
    SNIPPET P1 ENDING P2 IS EVALUATED AS "Name";
    For information on backwards compatibility, refer to the user manual, section “WCET Contribution of Code Snippets”.
  • The annotation to add execution time to the standard instruction timing has become more powerful: 
    instruction <PP> additionally takes <time>
 [and features dispatch_stall = 1] ;
    where <time> is now a generic expression of type machine cycles as described in the user manual. Conversion from old syntax is explained in the user manual as well.
  • New assert annotation allows specifying certain conditions (e.g., values of registers or memory cells) that hold at certain program points: 
    assert instruction "R" is entered with always (r5 == 5);
    For further information, refer to the user manual.
  • The max-unroll parameter can now be set for individual loops: 
    loop "R" + 1 loop max 20
and max-unroll = 10;
    Note that the local max-unroll parameter overrides the global specification. For further information, refer to the user manual.
  • AIS no longer allows empty strings as program point names. Errors will be issued for annotations containing such empty names.
  • The comma after “interproc flexible” is now optional. This was a common typo and is now official syntax.
  • The user can now disable the target check of control-flow changing instructions: 
    instruction <PP> skip target check;
  • Changes to expressions:
    • New expression inf stands for a value larger than any representable number. undef is now deprecated and should be replaced with (-inf..inf).
    • New switch expression.
    • Space units such as bytes can be used in expressions.
    • Time units such as cycles can be used in expressions.
    • Operands of unary functions must be parenthesized in expressions.
  • Am486, LEON2, LEON3, MPC55xx, MPC603e, MPC7448(s), MPC750(s), MPC755(s), TriCore: cache flushes at not-analyzed code snippets can now be disabled via 
    global disable_external_cache_flush = 1;
  • Am486, i386, LEON2, LEON3, MPC55xx, MPC603e, MPC7448(s), MPC750(s), MPC755(s), TriCore, V850: pipeline flushes at not-analyzed code snippets can now be disabled via 
    global disable_external_pipeline_flush = 1;
  • MPC603e, MPC7448(s), MPC755(s): timing properties of asynchronous memory can now be specified in bus cycles or external cycles.
  • HC11, HC12: new annotations for interrupt routines via SWI. Old SWI annotations are deprecated and should be rewritten. For further information, refer to the user manual, section “Software Interrupts (SWI)”.

Decoding

  • Improved encoding handling: AIS files and source files are first tried to be read as UTF-8, else fallback to CP1252 (Latin).
  • If register values are specified or detection of them is disabled, decoding will skip output about them.
  • Fixed source line counting in the Files view.
  • Improved GNAT support, per default assuming no exceptions occur and marking them as infeasible and not analyzed.
  • Prefer DWARF2 over DWARF1, if both debug infos are found.
  • Better error reporting if switch table patterns cannot read the table from the executable.
  • Detected irreducible loops and recursions are reported as info messages.
  • Exception routines from ADA can now be excluded from the analysis.
  • For the GHS compiler, short versions of symbols can now be used, e.g. test instead of test@abc/def/testapp.c
  • AIS:
    • AIS labels can be forced to replace routine names in graphs and report files: 
      LABEL R = force L;
    • The label annotation can now define ranges, too: 
      LABEL a .. b = s;
  • ARM7:
    • Implemented handling of __ARM_switch8.
    • Internal compiler generated symbols such as $p are hidden in the symbol table.
    • Improved decoding of various switch table types.
    • Allowed analysing __rt_lib_init.
    • Improved detection of call instructions.
    • Improved decoding for multiply-instructions.
    • Improved mnemonics for some instructions.
    • Improved handling of unresolved computed branches and annotations resolving computed branches.
    • Improved decoding of computed branches.
  • C16x:
    • Improved decoding for indirect movb and SFR/ESFR bit manipulation.
    • Added # before segment number in assembly string for exts and extsr.
  • C33: correct order of registers of parallel multiply instructions.
  • H8: added support for ELF files generated by H8/GNU GCC.
  • HCS12:
    • Improved support for HCS12X with Metrowerks/Codewarrior compiler.
    • Removed page restrictions for special HCS12X derivates.
    • bgnd instruction changed from “unresolved computed call” to a “trap” with the name “bgnd”.
  • M68020:
    • Improved decoding of moves.
    • Added support for static data symbols from AOL files: 
      => SYMBOL@static@FILENAME
    • Added possibility to differentiate labels from AOL files in different ADA sources: 
      => LABELNAME@label@FILENAME
  • PPC:
    • Improved decoding for loops starting at routine entry.
    • More switch table patterns (DiabData + AdaCore GNAT).
  • SPARC (LEON2, LEON3):
    • Improved switch table patterns.
    • Improved trap handling.
    • Detect returning calls immediately.
  • V850:
    • Improved switch table patterns.
    • Support for full 29-bit code address space for the E2 core and full 26-bit code address space for the E1 core.
    • Improved return handling.
  • X86:
    • Enhanced handling of descriptor tables.
    • Improved decoding of switch tables.

Loop analysis

  • Improved handling of nested loops.
  • PPC: special TargetLink/SCADE loop patterns for value analysis are now activated by options in the GUI ( “General” → “Loop Analysis”) rather than by license features.

Value analysis

  • Much faster extended feasibility analysis.
  • Improved precision of extended feasibility analysis.
  • Improved precision by using minimal loop bound to calculate infeasible paths.
  • Improved handling of the “routine <programpoint> is interesting” annotation.
  • Improved handling of the “area <area> is watched” annotation.
  • Greatly improved check for target feasibility on computed branches, computed calls and return instructions. This improvement is not yet available for HC12/HCS12, C166, and x86. For further information, refer to the user manual, section “Target Check”.
  • ARM: more precise handling of guarded code.
  • M68020: improved precision for M68k bitfield instructions.
  • V850: added support for V850E/FK3-H (PD70F3469) and V850E2/Fx4-H (PD70F3501).
  • X86:
    • Improved precision for load segment limit instruction.
    • Improved precision for memory accesses caused by gate calls with and without privilege level changes.

Stack analysis

  • StackAnalyzer will report all known strongly connected components (SCCs) if unbounded recursion is found.

Path analysis

  • “snippet ... is evaluated as ...” supported by predan/predpathan.

Pipeline analysis

  • Am486:
    • Optimized processor model thanks to further validation with hardware traces.
    • Added support for new instructions verified via measurements:
      • normal far call/return
      • far call/return through callgate, same privilege level
      • far call/return through callgate, different privilege levels
      • iret, same privilege level
      • lsl
  • ARM7:
    • Improved precision of the UCB analysis.
    • Dropped support for FLASH modules.
    • Added support for disjoint instruction and data caches (TimingExplorer).
    • Added support for burst accesses (TimingExplorer).
  • C16x:
    • Improved analysis precision.
    • Improved analysis runtime and memory consumption.
  • HC11: improved analysis runtime and memory consumption.
  • LEON2:
    • The instruction burst fetch can now be disabled in the cache configuration dialog. This corresponds to the instruction burst fetch (IB) bit in the cache configuration register (CCR).
    • Improved precision of the cache fill operation when burst-fetching instructions.
  • M68020: added support for priviledged move instruction reading from or writing to the status register. Reduced overestimation of the fmove instruction reading from or writing to the MPU data register.
  • MPC5xx:
    • Memory areas with external transfer acknowledge are now supported. The timing properties of such areas must be specified in AIS.
    • Improved the processor’s internal memory model.
    • Fixed handling of multiple subsequent tail instructions.
    • Implemented the USIU burst feature. Added support for eight-word bursts.
  • MPC55xx:
    • Improved data cache analysis precision.
    • Improved the precision of the analysis with respect to memory accesses targeting the internal FLASH module.
  • MPC7448: improved handling of external program snippets.
  • MPC603e, MPC755, MPC7448:
    • Added support for more than 32 persistence scopes.
    • The user may now specify timing ranges for single memory accesses instead of a precise number of cycles.
  • V850:
    • Added support for V850E/FK3-H (PD70F3469) and V850E2/Fx4-H (PD70F3501).
    • Improved the processor’s internal pipeline model (V850E/PHO3).
    • Improved handling of external program snippets.