a³ release 10.12

New targets

  • New a³ for MPC603e with universal DDR controller support.
  • New a³ for PPC750 with universal DDR controller support.
  • New a³ for x86 with StackAnalyzer for x86 and x86rm.

Qualification Support Kits (QSKs)

  • QSKs are now available from the a³ GUI via “Help” → “Qualify…” (see screenshot).
  • Extended the AIS expression semantics tests by the usage of:
    • the sint/uint cast operators;
    • the exactly== operator;
    • the (-inf..inf) construct.
  • Added tests for:
    • parametric loop bounds;
    • user register values;
    • path exclusion based on user register values;
    • loop bound with time limit;
    • verifying that irreducible loops cannot be handled by loop annotations but by flow constraints.
  • The QSK for StackAnalyzer for PowerPC with gcc-4.1.2 now includes hardware stack measurement tests.

a³ toolchain

32-bit and 64-bit Linux only: Programs now report a backtrace if they abort. Please include this backtrace when contacting support.

a³ GUI

  • Improved performance for projects with many analyses.
  • Message views are no longer separate items in the left-hand navigation panel. They have been merged into the corresponding Analyses views. (See screenshot.)
  • Clicking on a link in an error message now opens a menu where you can select whether you want to go to the corresponding place in the source or disassembly view (see screenshot).
  • The colors used for highlighting in the AIS editor can now be customized.
  • General improvements to the toolbar and the view handling.
  • Improved handling of register values. Only analysis integral registers such as the stack pointer are configurable in the target configuration page of the GUI. The Registers view has been removed, all additional registers must be specified via AIS annotations. The AIS Wizard is extended to help with this. New symbol name ":analysis_start" can be used for that with instruction label: 
    ":analysis_start" is entered with r12 = 1
  • The shortcut for stopping analyses is now F4. The previously used Ctrl + Esc is no longer supported.
  • Improved Configuration view (see screenshot).
  • For architectures with several stacks, the result of a stack analysis in a computation can be referenced using the keywords “user” for the user stack and “system” for the system stack. Example: 
    select(#StackAnalysis, user)
  • There is no longer a separate item “Registers” in the left-hand navigation panel. Instead, all registers must be annotated via AIS, either manually or with the help of the AIS Wizard. (See screenshot.)
  • Improved address value input fields (see screenshot).
  • The editor always displays and keeps up-to-date the information about which parts of the code are infeasible or contribute to the WCET or maximum stack usage.
  • The debug views correctly display the addresses of variables that are relative to the contents of a register.
  • Better handling of the unbounded/infeasible result for computations.
  • Existing XML result files are now loaded upon opening a project, to display results of already performed analyses.
  • Improved visualisation:
    • by searching for “unresolved” the user gets all unresolved computed branches and calls as results;
    • improved performance of the embedded graph viewer;
    • improved source code visualisation.

AIS

  • The user may now override the default unroll parameter at loop level.
  • Improved annotation export for the “Export project” option.
  • Changed the format of the mem annotation to better match the format of other functor-like AIS annotations:
    • mem <unit> (<addr>) is now written as mem (<addr>, <unit>).
    • mem <byte_order> (<addr>) is now written as mem (<addr>, <byte_order>).
  • New annotation “always returns” enables specifying that an external routine always returns and therefore is not a possible end of the program.
  • The new “:analysis_start” label enables referring to the analysis entry symbolically in AIS files.

Decoding

  • Program headers are ignored by default for section creation. Only if no valid sections are found for each program header a section is created. You can switch back to the old behavior by checking “Always Read Program Headers” in the advanced options.
  • Improved pattern matching for switch table detection.
  • Better handling of ambigious names for one address, e.g. global symbol names are now preferred.
  • exec2crl now lists all recursive routines.
  • GHS compiler: short function names are now preferred for graph visualisation, e.g. “test” instead of “test@C:/test.c”. Long names are still used in annotations and elsewhere, when using a short name would introduce ambiguity.
  • ARM7: removed unnecessary destination register for one MOV variant.
  • Simplified mnemonics of VLE rwlinm instructions are now correctly inferred. (Previously, e_rlwinm rA,rS,n,0,31-n was displayed as slwinm rA,RS,n instead of slwi rA,RS,n.)

Stack and value analysis

  • Improved precision if memory accesses are unsharp, by reading all possible values and combining them up to a certain threshold.
  • The option “Do not analyze values of memory cells” is now honored by StackAnalyzer.
  • Improved warning messages about possible targets of unresolved computed calls.
  • Improved precision of the bitwise-and operator.
  • Performance improvements for the analysis of unrolled loops with many contexts.
  • HCS12: value analysis no longer determines memory accesses for computed jumps.
  • M68020: improvements to the btst instruction.
  • PowerPC:
    • improved precision for multiplication with immediate constants;
    • improved automatic loop detection for TargetLink-generated code;
    • restricted annotations are now used during analysis time to improve the precision of write operations to memory;
    • interactive value analysis now also shows the contents of the processor status flags updated by comparison operations (the flags are usually Negative, Carry, Zero, and Overflow).
  • V850:
    • improved precision of loop analysis;
    • improved annotation handling for mirrored memory areas.

Path analysis

  • Warnings about unbounded loops or recursions are now only information messages, as they may be bound by flow constraints.
  • Prediction file base path analysis: massive speedup of poptimize2p for the case of extensive splitting/joining in basic blocks.

Cache and pipeline analysis

  • Unresolved computed calls and branches are now handled as potential program exits for pipeline analysis, in addition to triggering warnings.
  • Improved persistence analysis.
  • Better handling of conflicts between memory annotations provided through the GUI and by the user.
  • M68020: improvements to the timing model of the M68020 processor (btst).
  • TriCore:
    • improved performance and memory consumption of the pipeline analysis;
    • now allowing higher waitstates for flash.
  • V850: improved handling of invalid memory area annotations.
  • MPC7448: improved selection of memory areas for accesses.
  • MPC755: support for handling of nop tail instructions.
  • PPC750:
    • support for handling of nop tail instructions;
    • state space optimizations caused by bus clock ratio splitting;
    • a 1:1 clock ratio between the processor core and the L2 cache unit is now assumed.

Visualization and reporting

Default configuration values are no longer shown in the textual report files.