New Statistics views |
Non-WCET cycles in XML |
Customizable AIS prefix |
The all-new Safety Manual for aiT, StackAnalyzer, and Astrée gives a detailed overview of DO-178B, DO-178C, and ISO 26262 with respect to checks for runtime errors, timing and storage-space constraints.
The verification objectives met by aiT, StackAnalyzer, and Astrée are listed. The qualification strategy for these tools based on QSK and QSLCD is detailed and shown to satisfy the requirements of the respective standards.
The Safety Manual is linked from the Welcome page and the Help menu.
Initial release of a tool coupling between aiT, StackAnalyzer, and TargetLink from dSPACE. The information stored in the TargetLink Data Dictionary is automatically exploited to provide details about interface and environment to AbsInt’s analyzers. This improves analysis precision and reduces manual effort.
The new AbsInt Toolbox lets Matlab/Simulink users launch aiT, StackAnalyzer, or Astrée analyses from TargetLink with a single mouse click.
Added launcher option -g
to combine suitable XTC requests
into a single call to a³.
Implemented support for OSLC export of analysis results.
before
is deprecated and should
no longer be used.instruction <pp> target preserves <..>
"
annotation that works analogously to "routine <pp> preserves <..>
".instruction "main" -> computed(1) calls: via ("FunctionTable") { struct: 16 byte; offset: 8 byte; } via { struct: 8 byte; offset: 4 byte; skipped: mem(address(element), 1) != 0; };
DW$L$
... from symbol table in coff files..UNCOMPRESSED.<name>
sections
to their .<name>
companions.tbb
table branches for ARM Thumb.ld.h
, 6-byte opcodeld.hu
, 6-byte opcodeld.w
, 6-byte opcodest.h
, 6-byte opcodest.w
, 6-byte opcodeMaximum self usage is [32..96] bytes
bbit0 x,n,offset
— branch if bit n in register x is zerobbit1 x,n,offset
— branch if bit n in register x is onebchg n,x
— test and change a bit in register/memory cell x (test result in Z-flag)bclr n,x
— test and clear a bit in register/memory cell x (test result in Z-flag)bset n,x
— test and set a bit in register/memory cell x (test result in Z-flag)btest n,x
— test a bit in register/memory cell x (test result in Z-flag)clr1 n,x
— test and clear a bit in memory cell x (test result in Z-flag)set1 n,x
— test and set a bit in memory cell x (test result in Z-flag)not1 n,x
— test and invert a bit in memory cell x (test result in Z-flag)tst1 n,x
— test a bit in memory cell x (test result in Z-flag)bt x,n
— test a bit in register/memory cell x (test result in C-flag)btc x,n
— test and complement a bit in register/memory cell x (test result in C-flag)btr x,n
— test and reset a bit in register/memory cell x (test result in C-flag)bts x,n
— test and set a bit in register/memory cell x (test result in C-flag)timing_in_bus_cycles
” for accesses to PCI.message_type
values consolidated and documented.