a³ release 17.10

Floating licenses

All tools now support floating licenses in addition to node-locked licenses. Any existing node-locked license can also be upgraded to a floating license if desired. Please contact support@absint.com with any questions.

Concurrent analyses

All tools now support running multiple analyses in parallel to save time. In batch mode, the desired concurrency limit can be specified using the option -j <number>. In the GUI, you can set a default limit in the Preferences. It can then be overridden for a particular analysis run by pressing and holding down the “Run All” button to select a new limit from a popup.

New targets

  • aiT for ARM now supports Cortex-M1/Milandr 1986VE1T.
  • StackAnalyzer and ValueAnalyzer for PowerPC now support 64-bit targets. For the purposes of licensing and pricing, the tools for 64-bit PowerPCs are distinct from those for 32-bit PowerPCs.
  • All tools for ARM now support the ARM Green Hills Ada compiler.

Introducing TimeWeaver

This all-new tool provides worst-case execution time estimates by combining static path analysis with timing measurements obtained from real-time instruction-level tracing. A preview version for PowerPC is now available on request.

C++ support

The new C++ Call Target Analyzer automatically resolves C++ virtual function calls by parsing the application source code.

Qualification Support Kits

  • New board-specific QSK packages are now available.
    • ARM: Milandr 1986BE1T, XMC4500, and TMS570LS3137.
    • C16x: c164ci-8em, xc167, and xc2387a.
    • C28x: TMS320F2808.
    • e200: MPC5554 and MPC5554.
    • e300: MPC8349EA.
    • i386: 386-sc.
    • LEON3: Gaisler VHDL model.
    • M68020: A2620.
    • MPC755: PPCEVAL-SP3.
    • MPC5xx: EVB-565.
  • Under Windows, the maximum path length limitation is now checked every time a test case is loaded.
  • For aiT and StackAnalyzer, XML result/report file consistency checks are now used in all suitable QSK test cases.

Windows support

Since release 16.10, all tools rely on DLLs from the Microsoft Visual C++ Redistributable for Visual Studio 2017. Starting with this release, the redistributable is included in the installer as an optional component, or can be installed manually at a later point from the directory share/3rdparty/vc.

DWARF view

Other GUI improvements

  • Improved performance when outputting a large number of messages.
  • The analysis progress is now also displayed in the Windows task bar.
  • Improved MSF file import with respect to TLB settings.
  • Improved validation of the “Expected result” field: floating-point numbers, including inf, are now only accepted for the chronometrical units. If your expected bounds do include inf, please check the manual on how to make it be assumed automatically (e.g. by writing 42 instead of -inf..42).

AIS2

  • Faster resolution of all annotations.
  • Improved resolution of complex area annotations.
  • Improved handling of 64-bit integer values in annotations like area contains.
  • Improved performance for area contains data annotations.
  • New AIS2 functor align(x, n) as a shortcut for x - (x % n). For example, to provide an initial stack pointer that is aligned to 16 bytes you can now use 
    align(address("STACK_SEG"), 16)
  • The count accesses annotation now supports providing a custom name for the corresponding area: 
    area 0xd0000000 to 0xd000ffff
count accesses: "DATA";
    The textual report will then contain information such as:
    Global Access Statistics:
    - Region 'DATA': 0xd0000000 .. 0xd000ffff
    - Port Width: 64bit
    - Reads: 461
    - Writes: 509
    - Unknown: 0
  • Improved handling of sets of constants during user expression evaluation. Annotations like 
    contains data: [ address(("EventTable"[])), address("HeadEvent") ];
    can now evaluate to a precise set of constants, rather than plain intervals, if the allowed set size is large enough.
  • It is now possible to write wrapped intervals as memory contents in "area contains" annotations. For example, the annotation 
    area 0x400281e0 width 1 contains {
    data: [0x00, 0xfe..0xff];
}
    will now be precisely used by the value analysis:
    memory areas considered as constant:
    1: [0x400281e0]
    [0x400281e0]:1 contains [0x00, 0xfe..0xff]
  • The takes X cycles annotation is now supported not only for loops but also for non-recursive routines: 
    routine "testFunction" {
    takes: 1234 cycles;
}
  • Trace partitioning can be be enabled routine-wide for all blocks with more than one incoming edge as follows: 
    routine <ProgramPoint> begin partitioning: trace;

Decoding

  • Improved support for and faster extraction of C++ DWARF debug info.
  • Faster switch and call table pattern matching.
  • Improved resolving of computed calls via multiple levels of indirection.
  • DWARF debug information is now used to verify function type signatures of annotated call targets. If a call annotation resolves to functions with different type signatures, the decoder will provide an info message, such as:
    Annotated call resolves to routines with mismatching type signatures:
    - 'f(int)'
    - 'g(int, int)'
    - 'h(double)'
    This could be due to an incorrect annotation.
    Please review your annotation.
  • Improved initial stack pointer value guessing.
  • Improved extraction of C++ class types from DWARF debug info.
  • ARM:
    • Improved call table patterns for GHS.
    • Improved switch table patterns for GCC and GHS.
    • Improved handling of tail merging optimizations for THUMB code.
    • Improved decoding of computed calls via multiple levels of indirections.
  • HCS12: Improved resolution of computed calls.
  • M68k:
    • XD Ada MC68020 Builder files now supported as AOL map files.
    • The decoder now supports the additional M68040 FPU instructions:
      • fdabs/fsabs
      • fdadd/fsadd
      • fddiv/fsdiv
      • fdmul/fsmul
      • fdneg/fsneg
      • fdsqrt/fssqrt
      • fdsub/fssub
      • fdmove/fsmove
    • Improved switch table decoding.
  • MSP430:
    • Support for 20-bit wide calls/branches via immediates.
    • Improved handling of indexed addressing in case of MPS430x instruction set and non-extended instructions.
    • Improved resolution of computed calls.
  • PowerPC:
    • Support for extended instruction set of e500v2 core (e.g. P2020).
    • Support for extended instruction set of e5500 (e.g T1042).
    • Improved switch table decoding.
    • Improved decoding of cache management instructions.
    • Support additional instructions from Debug APU, Enhanced Reservations APU, Volatile Context Save/Restore APU and Cache Bypass Storage APU.
  • TriCore: Improved GCC switch table resolving.
  • V850:
    • Extended decoder to support CVTF.HS, CVTF.SH, FMAF.S, FMSF.S, FNMAF.S and FNMSF.S.
    • GHS: Improved handling of compiler-generated routines.
  • x86: Improved resolution of computed calls.

Stack and value analysis

  • Improved precision of:
    • bit search operations,
    • zero extension operations,
    • the relational domain for complex expressions,
    • the array heuristic for arrays with an element size that is not a power of two.
  • Arrays with one-byte sized elements are now skipped for array heuristics.
  • Improved loopy analysis for loops with small loop counter ranges and for the case of leaving the signed/unsigned range and wrapping around.
  • PowerPC: Support for 32-bit execution on 64-bit hardware.
  • V850: Improved overflow flag handling.

Cache and pipeline analysis

  • ARM Cortex-R: Improved handling of misaligned accesses.
  • M68020: Improved model for multi-step full-range accesses.
  • PowerPC: Improved handling of synchronization instructions.
  • MPC755/MPC755s/PPC750: Improved handling of tw/twi instructions.
  • x86: Improved calling conventions for x86-64. Assuming more registers to be callee-safe and some standard stack effects.

Statistics and reporting

  • Improved reporting of accessed variables.
  • More accurate counting of full-range accesses without alignment information.
  • The Statistics view and the report files show the number of infeasible edges per routine.
  • The context sensitive WCET path XML output is extended with cache hit/miss information.
    • <wcet_edge source_block="b183" source_context="r180_c0" 
           count="1" cycles="55" edge_cycles="55" 
           target_block="b274" target_context="r180_c0">
  <wcet_cache_infos>
    <wcet_cache_info routine="r180" type="icache" hits="14" misses="9" />
    <wcet_cache_info routine="r180" type="dcache" hits="2" misses="2" />
  </wcet_cache_infos>
</wcet_edge>
  • Computation expressions are printed to the XML report even in case of evaluation errors.

Graph visualization

  • The new checkbox “Exclusive” next to the “Recursion” dropdown enables you to hide all parts of the graph that don’t belong to the selected recursion. If no recursion is selected, clicking the checkbox hides all parts of the graph that don’t belong to the worst-case path.
  • Improved GDL visualization when no source code is available.
  • The Control-Flow Visualizer now creates GDL in batch mode.
  • Improved crash recovery.