aiT for ARM now supports Cortex-M0 (STM32F0DISCOVERY)
All tools for ARM now support the Wind River Diab C/C++ ARM compiler
and LLVM/Clang-based compilers. This also includes support for the HighTec ARM toolchain.
All tools for x86 now support LLVM/Clang-based compilers.
The C++ Call Target Analyzer now also uses the LLVM/Clang 7 toolchain.
Improved performance
Decoding is now combined with the stack/value analysis into a single analysis phase,
refered to as the Instruction Stream Analyzer (ISA).
Optimized memory usage of the GUI and improved performance of Statistics views.
Improved handling of large XTC files, and of XTC files with multiple requests per CPU.
Improved performance for projects with many analyses, and improved feedback during loading of large projects.
Extended DWARF support
Added support for DWARFv5.
The debug information is now read significantly faster, especially for C++.
Improved handling of broken debug information.
The DWARF view now shows all class, structure, typedef and union types.
The base type names in the debug information are now normalized
to be consistent across different platforms and compilers.
Unified context settings
The default context specification is now the same for all analyses:
Loop 'Proc0.L1': fully unrolled in all contexts with [2] iterations
Loop 'Proc0.L2': libloopy matches in all contexts with [3] iterations
Infeasible loop contexts will be ignored for later reporting in loop bound GUI
and report statistics, too.
ResultCombinator
New operator sum(@GROUPID) to sum up the results of all items within an analysis group.
ResultCombinator now also supports TimeWeaver analyses.
General improvements
Improved memory usage of the GUI.
Improved performance for projects with many analyses.
Improved feedback during loading of large projects.
Improved performance for large XTC files.
Improved handling of XTC files containing multiple requests per CPU.
Improved usability of the "Restrict XML tags" tree view.
Improved handling of annotation locations for duplicated instructions.
Improved "show source" for loops.
Introduced "Add annotation" context menu entry for context-based statistic views, such as "WCET (context)".
Improved input field for multiple executables.
Improved progress reporting during starting of analyses for large projects.
Improved syntax highlighting for C/C++ and the AbsInt annotation languages.
Improved search in view for XML files.
Disassembly view shows the existence of code holes and their content.
AIS2
New functors:
index_of_parameter(<name>) to determine the index of a parameter,
number_of_parameters() to determine the number of parameters of a routine
The information is taken from function definitions found in the DWARF debug information (if available).
Example:
# assert that the last parameter of a function is called n
routine "tableLookup" {
assert enter with: index_of_parameter("n") == (number_of_parameters() - 1);
}
New annotation scope: you can now specify for-loops in AIS2
to annotate memory area contents that depend on the array element index. Example:
# provide memory contents for dynamically initialized data structure
for ("index" : 0 to entries("MK_taskCfgTable") - 1) {
area (("MK_taskCfgTable"[] { index: var("index"); } ."nu")) {
contains data: var("index");
}
}
The default context specification is now the same for all analyses:
mapping {
max length: 2;
default unroll: 2;
}
Previously, the default for stack analysis was
mapping {
max length: 2;
default unroll: 1;
}
and for all other analyses except TimeWeaver, it was
mapping {
max length: inf;
default unroll: 2;
}
You can use the above annotations to switch back to the old settings if needed.
TriCore: more memory properties are now annotated automatically.
Instruction Stream Analyzer
The decoding, stack analysis and value analysis are now combined into a single analysis phase,
refered to as the Instruction Stream Analyzer (ISA).
For XML reports, decode, value_analysis, and stack_analysis
are now all united in cfg_value_analysis.
Stack and value analysis
Higher precision of the value analysis, thanks to improved widening.
It now collects comparisons and only tries to widen up to the guaranteed bound.
Higher precision for callee-save register handling.
Improved sharpening via relational information for user-annotated memory cells.
Improved handling of external routines, keep calling contexts separated for them
to avoid imprecision.
The decoder checks if computed (tail) calls hit functions with different signatures
and reports this accordingly.
Improved heuristics to resolve computed calls via arrays using DWARF debug information.
Improved precision of relational analysis by exploiting more equivalence information.
Improved loop analysis for loops with counters in memory.
Improved iterative decoding if the control flow targets are aligned.
If symbols are known for the aligned targets, they will be kept separate
like for sets of constants.
Improved precision of stack relative memory information.
When data is read from writable or unreadable sections,
the decoder provides an additional hint to declare the accessed area
as volatile. Declaring memory areas as volatile prevents the decoder
from accessing their data to reconstruct the control flow.
ARM:
Added support for ARMv8 AArch32 instructions.
Added support for cryptographic extension in AArch64 mode.
General improvements of the decoder, and improved switch table decoding for GCC specifically.
Improved handling of guarded execution.
Improved target alignment for indirect branches with mode switch.
C16x: improved precision of CP update handling.
PowerPC: improved switch table decoding.
TriCore: improved handling of switch tables.
V850:
Improved decoding of computed returns.
Improved SDA guessing for GHS.
FERET and EIRET now handled as end of program.
Cache and pipeline analysis
Improve performance of generic TimingProfiler pipeline.
Improve memory consumption and analysis time for large tasks with short call-string settings.
RH850: Improved timing analysis for data flash accesses.
C++ Call Target Analyzer
Now using the LLVM/Clang 7 toolchain.
Trace conversion
Support for the Infineon MTV TAB trace format.
Interactive MCDS tracing via Infineon DAS on TriCore AURIX devices.
Improved interrupt handling and trace coverage for PPC NEXUS traces.
Task switches can now be detected by specifying the memory cell that contains
the current active task ID. You can specify using the global attribute running_task:
Routines can now be excluded from the analysis using the annotation not analyzed.
The analysis then only considers the trace time for these routines.
Traps are now handled like external routines.
Improved handling for the GHS code factor optimization.
TimeWeaver analysis
Performance improvements for trace-based path analysis.
Improved loop scaling conflict detection.
Traced execution times spent inside routines declared as external
(using not analyzed) are now accounted for the annotated routine
instead of the calling routine.
Implemented support for overriding traced execution times of not-analyzed routines
via the takes annotation.
The analysis results can now be used in ResultCombinator.
Extended statistics
TimeWeaver statistics now include a polar chart view for trace segment and duration of interrupts.