a³ Release 20.04
New compilers
* PowerPC: Support for DDC-I SCORE compiler.
* RH850/V850: Support for Renesas CS+ compiler.
Qualification Support Kits
* New compiler-specific QSKs for:
* StackAnalyzer for ARM with ghs-2019.1.4-arm and ghs-2019.1.4-thumb
* StackAnalyzer for ARM with keil-3.1.0.939-arm and keil-3.1.0.939-thumb
* StackAnalyzer for PowerPC with diab-5.8.0.0p6
* StackAnalyzer for PowerPC with ghs-5.2.4
* StackAnalyzer for PowerPC with score-3.7.1
* aiT for e200 with diab-5.8.0.0p6
* aiT for e200 with score-3.7.1
* New board-specific QSK aiT for MPC5567
* Eval runs in test cases of compiler-specific packages
now also take the number of blocks/instructions per routine into account.
* Additional test cases:
qk_ais2_number_of_parameters
qk_ais2_index_of_parameter
qk_ais2_context_specification_value_partitioning
qk_ais2_value_set_size_limit | all architectures |
| qk_setting_additional_wcet_analysis_starts_skip_main | i386, C16x |
| qk_setting_local_worst_case | C16x, M68020 |
| qk_setting_extract_annotations_from_source_files | i386 |
* Enhanced qk_ais2_context_specification_trace_partitioning
for routine-wide trace partitioning tests.
Improved license handling
ValueAnalyzer license tokens are now only consumed
by standalone ValueAnalyzer analyses and analyses that have
the "Enable ValueAnalyzer features" option enabled.
Integration with dSPACE TargetLink
Improved Binary Level Analyzer Support in the AbsInt Toolbox for TargetLink.
Other improvements
* HCS12: Changes to the handling of paging and memory mapping.
All HCS12 derivates are now assumed to be paged for the annotations
and the memory map is now specified in the UI, not the AIS file.
* Improved handling of configurations.
GUI
* Improved handling of interactive analyses. Analysis results graphs can now be opened
and closed while an interactive analysis is still running. For this purpose there is
now a dedicated context-menu entry.
* Multiple analyses can now be cloned at once via the context menu.
* Improved ORTI project importer to support ORTI files with KOIL and OSSEMANTICS
version number v2.3 according to ORTI SMP proposal v4.
* Generalized ORTI project importer to support C expressions in task stack attributes.
* Improved handling of analysis entry point picker.
* Improved handling of messages with references to multiple locations
in the control-flow graph, source code, etc. Each message line
can now have multiple locations attached to it.
* Improved handling of detached views.
* Improved location handling in message view: location lines
will provide a context menu for precisely the current location,
rather than for all locations of the message.
* Improved loading of workspaces.
* The GUI is now more desktop-theme aware to better blend into non-default color schemes.
* Improved starting of parallel analyses.
Even if analyses are already running, it is ensured that newly started analyses
run as soon as the limit allows.
* Improved import of APX files generated by older tool versions.
* Improved message printing for some messages referencing contexts.
* Improved handling of analysis dependencies.
* The GUI now offers a context menu when double-clicking messages
with associated locations (such as call graph locations,
AIS file lines, source code lines), if no appropriate view is currently active.
* e200: the hardware configuration view now provides an annotation hint
for configuring cached memory areas.
ResultCombinator
The context menu of the ResultCombinator edit field now provides
analysis result names for easier insertion.
Visualization & results
* Timing analyses can report the cache misses per basic block
to the XML report file, including the address ranges of the accesses.
This option can be set under Setup → Reporting → XML Reporting →
Show per context info in XML report → Output cache statistics in XML report.
Example output:
<pipeline_cache_statistics>
<pipeline_cache_statistic block="d1_b49" context="d1_r276_c0">
<pipeline_cache_miss type="dcache" min="0x7fac" max="0x7fac" />
</pipeline_cache_statistic>
<pipeline_cache_statistic block="d1_b77" context="d1_r74_c0">
<pipeline_cache_miss type="icache" min="0x21c" max="0x21c" />
<pipeline_cache_miss type="dcache" min="0x7fdc" max="0x7fdc" />
</pipeline_cache_statistic>
</pipeline_cache_statistics>
* Variable usage statistics can now be exported into the XML report file
by enabling "Output variable usage statistics" under
Setup → Reporting → XML Reporting.
Example output:
<wcet_variable_usage>
<variable name="Array1Glob" address="0xf0004b4c" reads="2" writes="3" />
<variable name="Array2Glob" address="0xf00022a8" reads="1" writes="5" />
<variable name="BoolGlob" address="0xf0004cf4" reads="1" writes="2" />
<variable name="Char1Glob" address="0xf0004cf0" reads="2" writes="1" />
...
</wcet_variable_usage>
* Likewise, object size statistics can now be exported into the XML report file
by enabling "Output object size statistics" under Setup → Reporting →
XML Reporting.
Example output:
<object_size>
<region type="memory" name="Total" count="123" code_size="13040" data_size="11920" total_size="24960">
<region type="memory" name="DSPR" count="9" code_size="0" data_size="52" total_size="52">
<region type="data" start="0x70000000" end="0x70000013" name="framework" count="1" code_size="0" data_size="20" total_size="20" />
<region type="data" start="0x70000014" end="0x70000017" name="eraydiv" count="1" code_size="0" data_size="4" total_size="4" />
<region type="data" start="0x70000018" end="0x7000001b" name="ksflex" count="1" code_size="0" data_size="4" total_size="4" />
...
</region>
<region type="memory" name="PFLASH" count="51" code_size="6118" data_size="100" total_size="6218">
<region type="data" start="0x70000000" end="0x70000013" name="framework" count="1" code_size="0" data_size="20" total_size="20" />
<region type="data" start="0x70000014" end="0x70000017" name="eraydiv" count="1" code_size="0" data_size="4" total_size="4" />
...
</region>
...
</object_size>
* Removed the call_graph tag of the XML report for output of call graph.
The information about caller and callee functions is now expressed via the tags
<call/> and <called_from/> that are output as children of the tag <routine/>:
<routine id="r123" address="0xff00" name="test" blocks="2" instructions="10">
<call routine="r1234" />
<call routine="r1235" />
<called_from routine="r245" />
<called_from routine="r246" />
...
</routine>
The routine attribute specifies the routine ID of the caller or callee.
* Implemented "go to caller/target" history for CFG visualizations
which can be used to jump to recently done "go to" operations in the visualization.
* Search in control-flow graph will cover linear addresses, too.
* The domains shown in the interactive value analysis can now be filtered.
* Streamlined output of timing results in textual report.
* The text report file view now has a table of contents on the left-hand side,
for faster navigation to the different parts of the textual report.
Information
* Improved section content view.
* The DWARF debug information view now shows
associated hardware register numbers instead of
the DWARF register numbers.
* The DWARF debug information view can now automatically generate
"area contains" data annotations for function pointers and
function-pointer arrays where the content specifies functions
of matching type.
Example:
area ("msg_handler_tbl"[]."handler") {
contains data: address(type("void(unsigned char *)"));
}
Annotations
* Regular expressions may now be used in any symbolic program point or area definition,
for example:
routine match("Proc[0-9]+") { ... }
* The scope of an if annotation can now be extended by an else (if) clause:
# short call string length for stack analyses
if (analysisType("stack_analysis")) {
mapping max length: 2;
}
# unlimited call string length otherwise
else {
mapping max length: inf;
}
* Program points that refer to the source code via source(<filename>, <line>)
are now resolved case-insensitively.
* The annotation location of routine calls: <...> is now propagated
to the affected instructions.
* The annotation instruction <pp> target not analyzed
now always has precedence over any annotation that resolves
computed control-flow targets.
* Improved handling of:
* NULL pointers for paged architectures
* computed returns
* program point offsets
* "try" annotation scopes
* for loop annotation scopes
* Improved heuristics to resolve source code locations to program points.
* Improved matching in annotations that refer to source code using the match functor.
Decoding
General improvements to iterative decoding.
Value analysis
* Improved analysis precision for memory accesses.
* Improved DWARF array heuristics.
* Improved location output for AIS2 expression evaluation.
* If at least one value assertion fails, ValueAnalyzer will emit a warning (#3140)
and the result will be set to "some assertion failed". Example:
instruction "select" -> 20 bytes {
assert always exit with: reg("r0") == 7;
}
If the value of r0 is 8, this assertion will fail.
The value analysis will then emit two warnings:
Warning #3087: In routine 'select', at address 0x10000560:
In context '..., 0x1000059c->"select"':
In "/tmp/test.ais", line 3, column 30:
Assertion failed (expression 1 of 1).
and:
Warning #3140: ValueAnalyzer detected potential assertion failures.
Please consider the report file for more information.
Stack analysis
* Modifications of the stack height to an unknown value may not lead
to an unknown global result anymore, in case the local modification
is on a backwards infeasible program path.
* The tool now reports if the configured stack area contradicts
the computed stack usage. Example:
Error #3175: More stack space used than available in the configured stack area:
* Configured stack area: [0xd0000000..0xd00009a8]
* Initial stack pointer: [0xd00009a8]
* Available stack space: 2472 bytes
* Used stack space: 24440 bytes
Results might not be worst-case.
Target-specific improvements
* ARM:
* Enhanced support for the GHS compiler version 2019.1.4
* Enhanced support for ARM RealView Compiler Toolchain version 3.1
* Improved handling of call tagret annotation for call instructions
that switch the instruction set.
* Improved decoding for privileged load/store multiple instructions.
* HCS12:
Improved automatic resolving of computed calls.
* M68k/ColdFire:
Support for the ColdFire MAC instruction set extension.
* PowerPC:
* Improved automatic switch table decoding for DiabData, GCC, and GHS.
* Special purpose registers are now assumed not to be modified by external routines.
An external routine modifying a special purpose register can be declared using
the annotation
routine <name> enter|exit with: destroy(reg("spr<id>"))
where <name> denotes the external routine name and <id>
the number of the special purpose register.
* SPARC:
Improved decoding of calls to routines that return an aggregate value
such as a C-language structure.
* TriCore:
* Improved assembly strings for mfcr and mtcr instructions.
* Improved stack and value analysis.
* DiabData: Improved handling of code-factoring optimizations.
* DiabData: Improved stack pointer and CSA register guessing.
Cache and pipeline analysis
* Improved performance of timing analysis by folding
the prediction file optimization step into the pipeline analysis.
* TimingProfiler now supports cache annotations.
* ARM:
* Improved Cortex-M0 pipeline analysis model by revised register dependency checking.
* Improved Cortex-R4/R5 pipeline analysis model.
* Cortex-R4: Improved modelling of SVC instruction.
* Cortex-R5: Improved modeling of instruction fetches that bypass the instruction cache.
* e300/Optimizer/MPC755/PPC/PPC750:
Increased analysis performance for the instruction cache modes
"Hit if unknown" and "Always unknown".
DWARF
Improved location reader allow more (global) variables to be
extracted from debug information.
C++ Call Target Analyzer
Updated to the LLVM/Clang 10 toolchain.
TimeWeaver analysis
* Improved trace parser speed by using multiple threads.
* Now supporting iSYSTEM winIDEA binary trace export format.
* Improved handling of Lauterbach FLOW export traces.
* Introduced mode-based analysis on trace-level. The new annotation
attribute "running_mode": <Expression> specifies which mode should be
considered for the current analysis. Example:
attribute "running_mode": (mem("ACTIVE_TASK_CLOCK") % 4) == 3;
Here, the trace parser only considers those trace snippets where the value
of ACTIVE_TASK_CLOCK satisfies the condition % 4 == 3. In this fashion,
mode-based TimeWeaver analyses can be performed without the use of
the value analysis. For this annotation to become effective, the input
trace data must contain information about memory write accesses
to the variables specified in the mem functor.
* Introduced automatic trace format recognition,
which allows for providing multiple trace files in different trace formats.
* Generalized trace parser for iSYSTEM winIDEA CSV traces.
* Infineon DAS trace parser now uses MCDS trace DLLs v1.0,
which requires DAS v7.1.8 (or newer).
* Improved handling of interrupts.
* Improved trace end detection.
* If the intersection between the analyzed and the traced loop bound is empty,
the analyzed loop bound is now used.
Trace validation
Improved speed of trace validation.
TimeWeaver GUI
* Added per-context trace coverage statistics.
* Per-context trace coverage statistics are now only available
if "Perform value analysis" is enabled under Setup →
Timing analysis → TimeWeaver
(default is enabled).
* Per-context trace coverage statistics are exported to XML report
if "Show per context info in XML report" is enabled.
* Additional context-sensitive trace coverage information output in text report.
Block addresses that are only traced in some but not all contexts are now printed.
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Last updated on 28 April 2020 by alex@absint.com. Copyright 2020 AbsInt.
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